The present invention relates to a semiconductor memory device and a precharge control method for precharging bit lines in a semiconductor memory device, and more particularly, to a semiconductor memory device having a plurality of precharge circuits for precharging bit lines.
Semiconductor memory devices read data from or write data into memory cells via bit lines. Following completion of such access operation, the semiconductor memory devices precharge the bit lines to a predetermined potential (precharge operation). For these semiconductor memory devices, a technique is required to increase the speed for precharging the bit lines and shortening the cycle time for accessing the memory cells.
Japanese Laid-Open Patent Publication 9-231758 describes an example of a semiconductor memory device having precharge circuits provided respectively for memory cell groups and a control circuit controlling the precharge circuits. The semiconductor memory device quickly precharges bit lines with the precharge circuits.
FIG. 1 is a schematic block diagram showing a conventional semiconductor memory device 1.
The semiconductor memory device 1 has a memory cell array 11. The memory cell array 11 is formed by rows and columns of memory cells 12 (in FIG. 1, the memory cells 12 arranged in the direction of the rows are not shown). The semiconductor memory device 1 has a plurality of bit line pairs, each bit line pair being connected to one of the columns of the memory cells 12 (in FIG. 1, only one bit line pair Bit/XBit is shown). The semiconductor memory device 1 further has a plurality of precharge/equalization circuits 14L, 14M, and 14U and a sense amplifier 15 which are connected to each bit line pair.
The semiconductor memory device 1 also has a timing control circuit 16. The timing control circuit 16 controls the timing for accessing the memory cells 12 in accordance with an input signal such as a clock signal CK, an address signal AD, or a control signal CNT. The timing control circuit 16 includes a precharge/equalization control circuit 16a for generating a precharge/equalization signal EQ.
The precharge/equalization circuits 14L, 14M, and 14U are respectively located at three different positions in the memory cell array 11, a closest position, a middle position, and a farthest position from the sense amplifier 15. The precharge/equalization circuits 14L, 14M, and 14U precharge the bit lines Bit and XBit to a predetermined potential in response to the precharge/equalization signal EQ provided from the precharge/equalization control circuit 16a. 
The operation of the semiconductor memory device 1 shown in FIG. 1 will now be described. The operation for reading data from the memory cell 12U located at the farthest position from the sense amplifier 15 will be described.
As shown in FIG. 2, when a clock signal CK is input to the timing control circuit 16 to start the read operation, data in the memory cell 12U is output to the bit line Bit. The data is transmitted to the sense amplifier 15 via an upper portion (U), a middle portion (M), and a lower portion (L) of the bit line Bit. The sense amplifier 15 amplifies the data transmitted to the lower portion (L) of the bit line Bit so that the data can be read. When a predetermined delay time elapses after the completion of the operation at the lower portion (L) of the bit line Bit that is close to the sense amplifier 15, the precharge/equalization control circuit 16a provides the precharge/equalization signal EQ to the precharge/equalization circuits 14L, 14M, and 14U. The precharge/equalization circuit 14L, 14M, and 14U respectively precharges the bit lines Bit and XBit in response to the precharge/equalization signal EQ.
Japanese Laid-Open Patent Publication 8-63971 describes another example of a semiconductor memory device having a sense amplifier and a precharge circuit located on opposite side of a memory cell array from the sense amplifier. In this semiconductor memory device, a signal generation circuit located close to the sense amplifier provides a precharge signal to the precharge circuit.